A Rudimentary Hardware MPEG Video Decoder

David Crandall

CSE 471 Honors Project

April 29, 1999

Dr. Das


For my honors project, I designed and implemented a rudimentary MPEG decoder using Synopsys VHDL. Given an MPEG bitstream, the decoder performs the following functions:

A full implementation of the MPEG decoding standard would have been very difficult to build in one semester. This decoder is a minimal implementation, and makes some assumptions about the MPEG bitstream. These assumptions and limitations include:

Figure 1a shows an sample frame output by my decoder. For comparison purposes, Figure 1b shows the same frame, as decoded by the Berkeley mpeg_play program.

Figure 1a (left) shows a sample frame decoded by my MPEG decoder;

Figure 1b (right) shows the same frame decoded by Berkeley mpeg_play

The MPEG-1 Video Standard

This section briefly describes the MPEG-1 video standard.

An MPEG video sequence is composed of several levels, and each layer has headers and data associated with it. The MPEG-1 layers are:

Instead of storing actual pixel values, MPEG streams contain the Discrete Cosine Transform (DCT) of each block. Although the DCT of an 8x8 pixel array still results in 64 coefficients, many of the coefficients become zero, so they can be more efficiently stored. Also, the coefficients can be quantized and still maintain an acceptable image quality.

To compress the images, MPEG uses various Variable Length Coding (VLC) schemes. VLC codes are used to encode some of the header information. The DCT coefficients themselves are encoded with Run Length Encoding (RLE) and then encoded as VLC. While these codes drastically reduce the amount of data in an MPEG video, they complicate the decoding process.

For reference, Appendix B of this report contains the structure of the layer headers, as well as some of the VLC encoding tables.

Implementation Details

This section describes the general implementation of my MPEG decoder.

With the exception of the D flip-flop, all portions of the decoder were implemented using structural VHDL code. The Synopsys design_analyzer program was used to generate VHDL source files for the PLAs.

The mpeg decoder itself is a VHDL entity called mpegdecode. Its inputs are an asynchronous reset, a clock, and a serial input line. Its outputs are an error line, which becomes high if mpegdecode encounters an error, and the hold signal. The decoder expects the MPEG bitstream to be sent synchronously, one bit per clock cycle, via the serial input line. At times, the decoder may be unable to keep up with the input. In this case, it will raise the hold signal, and the device providing the input stream must wait until hold returns low before sending more bits.

The following describes the individual circuit blocks that make up the MPEG decoder. All of the source code described is attached to this report as Appendix A.

Results and Conclusions

Figure 1 shows a sample output image from the decoder. To obtain this, a simulation file, attached in Appendix A, loads the MPEG data into the input unit's memory, and then begins the simulation. Whenever the macroblock unit's signals indicate that a block has been parsed and reconstructed, the simulation file dumps the contents of the register array to a file. A simple C program, sim2rgb.c, converts these pixel values into an image in RGB format.

This encoder would be very fast if implemented in hardware. However, it is very, very slow to simulate using Synopsys VHDL. Processing the single image frame shown in Figure 1 requires nearly three hours of processing time on the Sun Sparcstations in 101 Pond Building. This made debugging the decoder very tedious and time-consuming. If I were to continue working on this project, I might rewrite the IDCT code to use behavioral logic instead of structural logic, since this would probably significantly reduce processing time.

The project could be improved with more time. With very little more work, output images could be in color instead of in grayscale. Support for P- and B-coded frames could be added. This would involve adding RAMs that would store the last and the next frames so that they could be used for the motion compensation. I could make the decoder be compatible with more MPEG sequences, by removing some of the current assumptions that it makes.

I learned a lot in this project. First, I gained a lot of experience using VHDL, and I learned many new things about it. Obviously, I also gained an intimate knowledge of the MPEG standard, and in basic concepts of compression and data coding. I learned more about how the Discrete Cosine Transform works, why it is used, and how it can be implemented. Finally, I learned a lot from struggling about how to implement parts of the decoder in hardware. For example, I spent a lot of time deciding on the best way to perform the VLC decoders. In short, this was the most difficult and time-consuming hardware project I've worked on, but it was also the most rewarding.


"Inverse Discrete Cosine Transform for MPEG Stream." http://www.cs.uow.edu.au/people/nabg/MPEG/IDCT.html

Mitchel, Joan, William Pennebaker, Chad Fogg, and Didier LeGall. MPEG Video Compression Standard. New York: Chapman & Hall, 1996.

Appendix A: Source Code

Appendix B: MPEG Coding Tables

Appendix C:

Algorithm for Inverse Discrete Cosine Transformation